- Doctoral Degree
- Master's Degree
- Integrated Library System
- Layout Design
As a member of the Library Technology Group in TMG/LTD/Advanced Design (AD), you will be at the vanguard of designing digital libraries (standard cells) on leading-edge Intel processes to meet density, performance, and power scaling goals of CPU and SoC products. AD serves as the design interface with the process development team, working out key design/process interactions for all new Intel processes. You will be responsible for pathfinding, benchmarking, design, validation and support of library collaterals.
Your responsibilities may include:
Work with process, device, and design teams to co-optimize the transistor characteristics and layout design rules to enable the design of new technology.
Define the circuit content that helps meet the performance, density, and power needs of the products.
Formulate and validate the reliability and RC conditions that meet the needs of the targeted library.
Deliver circuit and layout collaterals for the test chips and products and define methodologies that enable seamless usage of library collaterals by any design team (internal or external).
Enable automation for library collateral release without compromising library and release collateral quality.
This is an entry level position and compensation will be given accordingly.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Candidate must possess a Master’s or PhD in Electrical or Computer Engineering or in a Physical Science.
Minimum of 6 months of experience in the following:
Digital, high speed VLSI design
Technology design rules, process development, and process integration
One or more of the following key areas: semiconductor device physics & analog circuit design principles, transistor-level digital design, physical layout design, reliability, auto place & route, library collateral integration.
Minimum of 6 months of experience in the Following
Computer Aided Design (CAD) tools like Cadence Virtuoso layout and schematic editor and other Industry standard tools.
Complex problems using computer algorithms and programming techniques.
Software development/programming in high-level languages (e.g. Java, SKILL, C++, TCL, Lisp, Scheme, Perl).
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....