- Laboratory experience
Allegro Microsystems is a world leader sensor company for mixed-signal sensor designs. Our sensors main applications are within traditional IC engine and self-driven electric automotive, consumer electronics, green energy industry, data center servers and industrial solutions. We are working with our partners to provide key solutions in growing new wave of applications that are at the center of self-driven cars, robotics and drone technologies.
Primary focus for this job position is modelling, verification and validation of mixed-signal sensors using Simulink v&v toolset and use of SystemVerilog and verification using Universal Verification Methodology (UVM-SV). As an integral part of the product development team, you will be exposed to variety of advanced tools based on specific application requirement. This includes Mathwork’s Simulink and Matlab scripting, programming in C for embedded processors.
Work with the system architects and create accurate design model.
Create verification plan and model system from design requirements/specification based on various sources including systems engineering specs, marketing documents, existing design specs
Use MBSE (model based system engineering) strategies to verify and validate the digital system for a mixed-signal sensor using Simulink V&V toolset and test harnesses
Use constrained random test benches and tests and assertion checkers using UVM and SystemVerilog
Analysis of verification results, functional verification coverage and debug of unexpected design behavior using Simulink V&V tools
Work on fault campaign on the design to fulfill ISO 26262 requirements on functional safety.
Script generation in Python and Matlab for model/test configuration as well as for processing results
Consult with design engineers on design for testability and coverage enhancement
Skills and Qualifications:
MS Degree in Electrical Engineering or affiliated disciplines.
Excellent communication, problem-solving and lab debug experience is required.
Experience with Verilog, SystemVerilog, Synthesis, lab prototyping and FPGA design and implementation.
Experience with Matlab and Simulink toolset is a strong plus.
Exposure to a higher level object oriented language is highly desired (C++, Python, etc.).