Date: 15-Jan-2022
Location: Auburn Hills, Michigan
Company: LTTS
Primary:
Lead debugging activities for determining Root Cause Analysis (RCA) for SW issues
Perform SW integration steps for generating beta efd file
Perform end-layer tests for official efd release to STELLANTIS - Design Release Engineer (DRE)
Initiate Component Version Verification Report (CVVR) for STELLANTIS – DRE
Update CVVR to include unresolved issues and deliver to STELLANTIS – DRE
Verify / demonstrate resolution of critical issues on bench, vehicle, Ply-wood Buck (PWB), Hardware in Loop (HIL)
Chair recurring and occasional meetings with STELLANTIS and Continental engineering, including software open issues, product requirements, and product validation
Capture SW communication log utilizing Vector CANoe tools from ply-wood buck, vehicles, VHIL, and bench with IC issues
Download EEPROM data / exceptions from IC with SW issues
Support coordination of Requirements Analysis Report (RAR) and Design Change Request (DCR) between STELLANTIS & Continental
Utilize STELLANTIS CDA tool for reflashing, capturing vehicle scan reports, reading exceptions / diagnostic trouble codes (DTC), and other evaluation functions
Update IC software and requirement issues in Continental JIRA portal
Updating EE portal issues, GIMs in their respective databases on timely basis until the issue is resolved