- Signal processing
- Communication skills
At Cirrus Logic, mixed-signal engineering drives our company. We develop high-performance, low-power signal processing solutions in audio, voice and haptics, delivering innovative end-user experiences and solving difficult challenges for new generations of mobile and consumer devices. While breaking the innovation barrier, we've also built an award-winning company culture, thanks to our extraordinary workforce and our ongoing efforts to champion and promote diversity, as well as our principles of equality and fairness in the workplace. Do you enjoy working alongside the industry's top engineers and solving sophisticated challenges for the world's top consumer brands? Join our team and help us continue to make this an exceptional place to work!
We are seeking creative and hardworking engineers to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. Additionally, we are seeking innovative individuals who are interested in this position which will play a vital role streamlining development methodology for our organization. We are proud of our exceptional environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!
You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs for audio processing applications
Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design
Independent Interpretation of analog circuit schematics into abstract models
Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
Collaborate with multi-functional teams to streamline chip-level integration
Performing regression debug support and other flow/infrastructure development
Required Skills and Qualifications
MS or higher in Electrical Engineering or Computer Engineering and 5+ years of verification experience preferably in mixed-signal products
Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification
Organized and detailed with strong communication skills
Possess outstanding analytical and problem-solving skills
Results-oriented and ability to operate in dynamic environment
Preferred Skills and Qualifications
Python skills would be highly desirable
This position is located in Austin, TX
Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.