Job Title: Senior DFT Engineer
Work Location: 100% remote / work from home
Full-time: Salary + Benefits + Bonuses
Summary:
You will perform various types of Design for Test (DFT) tasks such as implement all the DFT modes of a design, including MBIST, JTAG, Scan and ATPG. Verify the DFT functional correctness of the design using industry standard simulation tools. Conversion of test vectors to ATE and assisting in silicon debug on the ATE.
Requirements:
- BSEE with 7+ years of DFT experience
- Implement test strategy for complex mixed-signal circuit designs and digital designs
- Experience with DFT tools from Synopsys, Tessent, and Cadence
- Experience implementing MBIST, JTAG (1149.6 and IEEE1687), scan insertion, and performing vector verification
- Experience in silicon debug and bring-up on ATE
- Good understanding of RTL design, Verilog and SystemVerilog
- Able to work independently on the above tasks and be the DFT owner for the design
- Test coverage and test cost reduction analysis
- Experience with test compression
- Scripting experience with TCL, Python, Perl
- Develop documentation and design specifications
- Excellent communications skills