- Bachelor's degree
- Doctoral degree
- Signal processing
- Analysis skills
What You Will Do:
At A llegro Microsystems we architect, design and deploy advanced technology mixed signal sensors. W e currently have opening s for entry level Digital design engineer s to join our expanding advanced sensor development team . This opportunity will allow an individual to contribute within the framework of a broader experienced analog, mixed-signal and digital team. We are looking for a motivated candidate that can leverage the group ’ s experience to begin quickly contributing to the success of the team.
The primary focus for the individual will be the using cutting edge tool s to design state of art sensors in Allegro’s Model Based Design flow for digital signal processing applications. As new product developer, you will be exposed to variety of tools based on specific application requirement, including Mathworks Simulink applications , embedded microprocessor coding , Matlab scripting, Verilog , System Verilog and Universal Verification Methodology (UVM).
Typical tasks for a Design engineer include:
Development of signal processing and control algorithms through system modeling from concept, prototyping, testing and validation to production
Traditional V erilog c odi ng / unit level verification of serial interfaces, microprocessor interfaces , SRAM, Flash, EEPROM and the register map
Analysis of test results, test coverage and debug of unexpected design behavior.
Synthesis of RTL with timing and area constraints
Writing and/or debug of Simulink models using Mathwork tools including Stateflow , HDL coder and digital signal processing tool box
Education and Experience Requirements
The successful candidate will possess a Bachelor's, Master s or a Doctorate degr ee in Electrical Engineering or a related discipline - E ntr y level with 3.0 + GPA.
Excellent communication, documentation, problem-solving and analytical skills are required.
Experience with the use of : Matlab , Simulink tool set , Verilog, System Verilog, Synthesis, DFT, UVM , embedded microprocessor and FPGA Design and implementation is a plus .
Exposure to a higher l evel object oriented language is highly desired (C++, Python, SystemVerilog , etc. ) . Any exposure to one of the structured verification methodologies is a strong plus.