Exegy is seeking an internal full-time hardware/firmware design engineer to develop high-performance data processing applications for the real-time financial data market. This is a full-time internal position based in St. Louis, MO. The engineer will be primarily tasked with implementing designs with SystemVerilog in FPGAs, implementing simulation testbenches and lab tests in SystemVerilog and C++, and implementing software APIs for hardware designs in C++.
If you are interested, please apply via the following link: https://exegy.bamboohr.com/jobs/view.php?id=109
No phone calls please.
No third party resumes please.
Knowledge, Skills and Abilities:
Experience with Quartus and/or Vivado.
Proficient in Verilog.
Comfortable with Python.
Comfortable with C++.
Comfortable with Linux.
Experience with Questa is a plus.
Experience with SystemVerilog is a plus.
Familiarity with financial markets is a plus.
BS or higher in Computer Engineering or Electrical Engineering and/or relevant industry experience.
Catered lunches on Fridays, social events, and volunteering to engage with the community
Weekly yoga, soccer games, and happy hours
A fridge of La Croix and other beverages (coffee, tea, energy drinks)
Ping pong, foosball, and shuffleboard tables
All your information will be kept confidential according to EEO guidelines.