Architecture and Design Engineer, Accelerator ASIC
Google
Madison, WI

About $96,000 - $120,000 a year

EducationSkills
Note: By applying to this position your application is automatically submitted to the following locations: Sunnyvale, CA, USA; Madison, WI, USA

Minimum qualifications:
PhD degree or equivalent practical experience.
Experience in logic synthesis, verification, timing closure, and physical design principles.
Experience applying computer architecture principles to solve open-ended problems
Experience applying engineering best practices (e.g. code review, testing, refactoring).

Preferred qualifications:
4 years of experience in FPGA/ASIC design and experience with ASIC development
Experience with computer arithmetic and with performance modeling. Experience with highly pipelined designs, and with multiple-clock-domain designs.
Proficiency in a procedural programming language (e.g. C++, Python, Go).
Knowledge of processor design, accelerators, and/or memory hierarchies. Knowledge of machine learning algorithms.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As an Architecture and Design Engineer for Accelerator ASIC, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery. cutting-edge data centers affecting millions of Google users.

You will be part of a team developing cutting-edge ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We're always on call to keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Understand the overall application of the chip, proposing and developing improvements in overall design.
Design and document one or more blocks of an ASIC, including functionality and timing.
Implement your designs in RTL (System Verilog or other HDLs).
Create simple test benches and debug complex logic simulations.
Work closely with software teams on functionality, interfaces, and documentation.
At Google, we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form.