Responsible for high performance block implementation (RTL to GDSII). Perform block level floorplanning, pin placement and power grid implementation.Implement block level placement, CTS and routing. Close the design to meet timing, power budget and area. Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements. Implement ECO’s to address functional bugs, timing and physical verification violations. Responsible for generation and maintenance of block level STA constraints. Run STA regression and publish timing status. Responsible for timing model generation and support successful integration of blocks into SOC.
5+ years of hands on experience in physical design of high performance CPU design with frequencies > 2 Ghz.
Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
Strong skills with Cadence Encounter.
Solid understanding of STA and timing constraints.
Experienced in working on advanced process nodes (16nm).
Strong expertise in Physical Verification to debug LVS/DRC issues at block level.